//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module	FRM_TJ0(
   input                         FRM_RESET,
   input                         FRM_TXCLK,

   input                         MPI_CLK,
   input                         MPI_J0_MODE,
   input[3:0]                    MPI_TJ0_ADDR,
   input                         MPI_TJ0_WE,
   input[7:0]                    MPI_TJ0_WD,
   output[7:0]                   MPI_TJ0_RD,

   input[7:0]                    TJ0_IN_TDATA,
   input[1:0]                    TJ0_IN_TFMCNT4,
   input[8:0]                    TJ0_IN_TFMCNT270,
   input[3:0]                    TJ0_IN_TFMCNT9,

   output reg[7:0]               TJ0_OUT_TDATA,
   output reg[1:0]               TJ0_OUT_TFMCNT4,
   output reg[8:0]               TJ0_OUT_TFMCNT270,
   output reg[3:0]               TJ0_OUT_TFMCNT9

   );

wire[7:0]               TJ0_TDATA;
wire[1:0]               TJ0_TFMCNT4;
wire[8:0]               TJ0_TFMCNT270;
wire[3:0]               TJ0_TFMCNT9;
reg                     TJ0_MODE;
reg[3:0]                TJ0_CNT;
wire[7:0]               TJ0_J0;

wire                    TJ0_RAM_CLKA, TJ0_RAM_CLKB;
wire                    TJ0_RAM_WEA, TJ0_RAM_WEB;
wire[3:0]               TJ0_RAM_ADDRA, TJ0_RAM_ADDRB;
wire[7:0]               TJ0_RAM_DINA, TJ0_RAM_DINB;
wire[7:0]               TJ0_RAM_DOUTA, TJ0_RAM_DOUTB;



  assign TJ0_TDATA[7:0]       = TJ0_IN_TDATA[7:0];
  assign TJ0_TFMCNT4[1:0]     = TJ0_IN_TFMCNT4[1:0];
  assign TJ0_TFMCNT270[8:0]   = TJ0_IN_TFMCNT270[8:0];
  assign TJ0_TFMCNT9[3:0]     = TJ0_IN_TFMCNT9[3:0];

always @( posedge FRM_RESET or posedge FRM_TXCLK ) begin
   if ( FRM_RESET==1'b1 )
      TJ0_MODE                                  <= 1'b0;
   else
      TJ0_MODE                                  <= MPI_J0_MODE;
end

always @( posedge FRM_RESET or posedge FRM_TXCLK ) begin
   if ( FRM_RESET==1'b1 )
      TJ0_CNT[3:0]                              <= 4'd0;
   else begin
      if ( TJ0_MODE==1'b0 )
         TJ0_CNT[3:0]                           <= 4'd0;
      else if ( TJ0_TFMCNT9[3:0]==4'd8 && TJ0_TFMCNT270[8:0]==9'd269 && TJ0_TFMCNT4[1:0]==2'd3 ) begin
         TJ0_CNT[3:0]                           <= TJ0_CNT[3:0] +4'd1;
      end
   end
end

  assign  TJ0_RAM_CLKA      = MPI_CLK;
  assign  TJ0_RAM_WEA       = MPI_TJ0_WE;
  assign  TJ0_RAM_ADDRA[3:0]= MPI_TJ0_ADDR[3:0];
  assign  TJ0_RAM_DINA[7:0] = MPI_TJ0_WD[7:0];
  assign  MPI_TJ0_RD[7:0]   = TJ0_RAM_DOUTA[7:0];

  assign  TJ0_RAM_CLKB      = FRM_TXCLK;
  assign  TJ0_RAM_WEB       = 1'b0;
  assign  TJ0_RAM_ADDRB[3:0]= TJ0_CNT[3:0];
  assign  TJ0_RAM_DINB[7:0] = 8'd0;
  assign  TJ0_J0[7:0]       = TJ0_RAM_DOUTB[7:0];
FRM_TJ0_SDP128_8_8                     INST_TJ0_RAM(
   .CLKA                               ( TJ0_RAM_CLKA ),
   .WEA                                ( TJ0_RAM_WEA ),
   .ADDRA                              ( TJ0_RAM_ADDRA[3:0] ),
   .DINA                               ( TJ0_RAM_DINA[7:0] ),
   .DOUTA                              ( TJ0_RAM_DOUTA[7:0] ),

   .CLKB                               ( TJ0_RAM_CLKB ),
   .WEB                                ( TJ0_RAM_WEB ),
   .ADDRB                              ( TJ0_RAM_ADDRB[3:0] ),
   .DINB                               ( TJ0_RAM_DINB[7:0] ),
   .DOUTB                              ( TJ0_RAM_DOUTB[7:0] )
   );

always @( posedge FRM_RESET or posedge FRM_TXCLK ) begin
   if ( FRM_RESET==1'b1 ) begin
      TJ0_OUT_TDATA[7:0]                     <= 8'd0;
      TJ0_OUT_TFMCNT4[1:0]                   <= 2'd0;
      TJ0_OUT_TFMCNT270[8:0]                 <= 9'd0;
      TJ0_OUT_TFMCNT9[3:0]                   <= 4'd0;
   end
   else begin
      TJ0_OUT_TFMCNT4[1:0]                   <= TJ0_TFMCNT4[1:0];
      TJ0_OUT_TFMCNT270[8:0]                 <= TJ0_TFMCNT270[8:0];
      TJ0_OUT_TFMCNT9[3:0]                   <= TJ0_TFMCNT9[3:0];
      if ( TJ0_TFMCNT270[8:0]==9'd6 && TJ0_TFMCNT9[3:0]==4'd0 )
         TJ0_OUT_TDATA[7:0]                  <= TJ0_J0[7:0];
      else
         TJ0_OUT_TDATA[7:0]                  <= TJ0_TDATA[7:0];
   end
end


endmodule
